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Date: Sun, 11 Aug 2013 19:38:41 +0400
From: Solar Designer <>
To: Sylvain Munaut <>
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board

Sylvain -

On Sun, Aug 11, 2013 at 03:41:07PM +0200, Sylvain Munaut wrote:
> Well, if you support all the peripheral, then this is going to be
> pretty big in term of logic usage. Like 50% of the fpga or so.

Oh, I thought this would be the case with 7010, whereas with 7020 I'd
expect over 2/3 of the FPGA resources to be left for our own use since
7020 is approx. 3x bigger than 7010.  No?

Anyway, at this time we're just starting to experiment.  We'd need to
maximize the number of crypto cores after we get at least one of them

> I've attached the uImage / device tree / BOOT.bin that I'm using now.
> They're built from the barebone design.
> Try with those.

Obviously, your message with the attached files was too large for the
mailing list, but I've received it fine and will share the files with

Thank you!


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