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Message-ID: <20261004171148.GJ23438@brightrain.aerifal.cx>
Date: Sun, 4 Oct 2026 13:11:48 -0400
From: Rich Felker <dalias@...c.org>
To: Alex Rønne Petersen <alex@...xrp.com>,
musl@...ts.openwall.com
Subject: Re: [PATCH] riscv: declare all vector registers as clobbers
of syscalls
On Sun, Oct 04, 2026 at 06:42:06PM +0200, Szabolcs Nagy wrote:
> * Szabolcs Nagy <nsz@...t70.net> [2026-10-04 18:15:57 +0200]:
> > * Rich Felker <dalias@...c.org> [2026-10-04 11:08:15 -0400]:
> > > Is there any way musl could plausibly be using upper range of sve
> > > registers? This is probably at present only a theoretical problem, but
> >
> > i compiled musl with armv8-a+sve and e.g.
>
>
> ok, i don't see any top bits actually used
> only clobbered, so unlikely for syscalls
> to cause trouble.
Yeah, here's what I'm trying to understand: doesn't any code wanting
to use upper bits need to be doing some runtime conditional on the
current size of the registers and either branching to multiple
versions of the code or somehow parameterizing what it's doing? And is
this something you can do purely with the ISA, or does it need some
libgcc-type hooks to report the size available to use? I'm trying to
understand how code that would use the upper bits even *could* arise,
so we can ensure that it doesn't.
Rich
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