musl - Re: [PATCH] riscv: declare all vector registers as clobbers of syscalls

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Message-ID: <20261004164206.GC3542221@port70.net>
Date: Sun, 4 Oct 2026 18:42:06 +0200
From: Szabolcs Nagy <nsz@...t70.net>
To: Rich Felker <dalias@...c.org>,
	Alex Rønne Petersen <alex@...xrp.com>,
	musl@...ts.openwall.com
Subject: Re: [PATCH] riscv: declare all vector registers as clobbers
 of syscalls

* Szabolcs Nagy <nsz@...t70.net> [2026-10-04 18:15:57 +0200]:
> * Rich Felker <dalias@...c.org> [2026-10-04 11:08:15 -0400]:
> > Is there any way musl could plausibly be using upper range of sve
> > registers? This is probably at present only a theoretical problem, but
> 
> i compiled musl with armv8-a+sve and e.g.


ok, i don't see any top bits actually used
only clobbered, so unlikely for syscalls
to cause trouble.

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