Follow @Openwall on Twitter for new release announcements and other news
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Fri, 12 Oct 2018 15:25:46 +0200
From: Jann Horn <>
Cc: Andy Lutomirski <>,, 
	Kernel Hardening <>, Thomas Gleixner <>, 
	Ingo Molnar <>, Borislav Petkov <>, "H . Peter Anvin" <>, 
	"the arch/x86 maintainers" <>, kernel list <>
Subject: Re: [PATCH] x86: entry: flush the cache if syscall error

On Fri, Oct 12, 2018 at 11:41 AM Samuel Neves <> wrote:
> On Thu, Oct 11, 2018 at 8:25 PM Andy Lutomirski <> wrote:
> > What exactly is this trying to protect against?  And how many cycles
> > should we expect L1D_FLUSH to take?
> As far as I could measure, I got 1660 cycles per wrmsr 0x10b, 0x1 on a
> Skylake chip, and 1220 cycles on a Skylake-SP.

Is that with L1D mostly empty, with L1D mostly full with clean lines,
or with L1D full of dirty lines that need to be written back?

Powered by blists - more mailing lists

Confused about mailing lists and their use? Read about mailing lists on Wikipedia and check out these guidelines on proper formatting of your messages.