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Date: Fri, 12 Oct 2018 10:20:25 +0100
From: Samuel Neves <sneves@....uc.pt>
To: Andy Lutomirski <luto@...nel.org>
Cc: kristen@...ux.intel.com,
Kernel Hardening <kernel-hardening@...ts.openwall.com>,
Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
bp@...en8.de, "H. Peter Anvin" <hpa@...or.com>,
"the arch/x86 maintainers" <x86@...nel.org>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] x86: entry: flush the cache if syscall error
On Thu, Oct 11, 2018 at 8:25 PM Andy Lutomirski <luto@...nel.org> wrote:
> What exactly is this trying to protect against? And how many cycles
> should we expect L1D_FLUSH to take?
As far as I could measure, I got 1660 cycles per wrmsr 0x10b, 0x1 on a
Skylake chip, and 1220 cycles on a Skylake-SP.
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