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Date: Fri, 12 Oct 2018 10:20:25 +0100
From: Samuel Neves <>
To: Andy Lutomirski <>
        Kernel Hardening <>,
        Thomas Gleixner <>, Ingo Molnar <>,, "H. Peter Anvin" <>,
        "the arch/x86 maintainers" <>,
Subject: Re: [PATCH] x86: entry: flush the cache if syscall error

On Thu, Oct 11, 2018 at 8:25 PM Andy Lutomirski <> wrote:
> What exactly is this trying to protect against?  And how many cycles
> should we expect L1D_FLUSH to take?

As far as I could measure, I got 1660 cycles per wrmsr 0x10b, 0x1 on a
Skylake chip, and 1220 cycles on a Skylake-SP.

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