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Date: Fri, 4 Oct 2013 06:32:58 +0400
From: Solar Designer <>
Subject: AMD GPU documentation (was: Daniel's weekly report #15)

Lukas, Daniel -

On Thu, Oct 03, 2013 at 06:31:14PM +0200, Lukas Odzioba wrote:
> I have two ideas at the moment:
> 1) can you split binary on parts using definitions in this header:
> I am curious how much of that match the real format.
> 2) Since CAL has separated compilation and linking phases, maybe we
> can somehow do something like pathing between those phases.
> You probably saw this:

BTW, speaking of AMD documentation on Southern Islands GPUs, these PDFs
might be relevant to the project as well:

In particular, page 165+ in SI_3D_registers.pdf describes "Shared
Program Registers", which includes things such as "Number of VGPRs,
granularity 4. Range is from 0-63 allocating 4, 8, 12, ... 256" - a
certain 6-bit value at a certain address (memory-mapped register?)
This might answer, negatively, my question on whether we can go beyond
256 VGPRs for a single work-item.


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