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Date: Fri, 9 Aug 2013 15:57:19 +0200
From: Sylvain Munaut <>
To: Katja Malvoni <>
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board

> But this is for rebuilding fsbl, shouldn't Ethernet be intact when
> generating and replacing bitstream?

Well it wasn't exactly clear what you rebuilt and from what, so I
assumed you rebuilt both the bitstream and the sd card BOOT.BIN.

The fsbl/kernel/device tree that was shipped with the prototype (and
that did HDMI) is meant for the ADI reference design and shouldn't be
used with the "barebone" bitstream in anycase. And if you use the
sd_card_files from the FTP for the barebone design, those have the
device tree issue preventing the ethernet to work at 100M.



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