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Date: Thu, 8 Aug 2013 23:23:25 +0200
From: Katja Malvoni <>
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board

On Thu, Aug 8, 2013 at 10:22 PM, Katja Malvoni <> wrote:

> I have no idea... First I'll make new bitstream from beginning. I added
> simple custom peripheral on current one to see if I'll be able to create
> bitstream when I add other stuff except Parallella prototype (bitstream was
> generated successfully). Deleting added stuff doesn't work as I expect it
> so I'll start from scratch (BTW, I used backed up .bit file for generating
> bin files I uploaded).

I created new ISE project and created bitstream. I diff new .bit.bin file
with old one - they are identical. I also diff my .bit file with one
downloaded from -
files are different. I have to change the name of io_clock_gen to be able
to create bitstream. Because of name change it is necessary to change
ewrapper_link_top.v:217 (creating instance of io_clock_gen). These are only
two changes I did to generate bitstream, the rest is done as described in
But I don't see how would these two changes cause the change of bitstream.


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