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Date: Thu, 8 Aug 2013 22:22:44 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board
> On Thu, Aug 08, 2013 at 09:49:12PM +0200, Katja Malvoni wrote:
> >
> http://forums.xilinx.com/t5/Embedded-Linux/Zynq-Loading-bitfile-into-FPGA-from-Linux-xdevcfg/td-p/237850and
>
This link is broken, this should be the correct one -
http://forums.xilinx.com/t5/Embedded-Linux/Zynq-Loading-bitfile-into-FPGA-from-Linux-xdevcfg/m-p/237872#M4062
On Thu, Aug 8, 2013 at 10:04 PM, Solar Designer <solar@...nwall.com> wrote:
> I tried loading this one, and it's a partial success: although I lost
> the ability to interact with the board via Ethernet (so I've
> power-cycled it to recover), the counter pattern on the LEDs was reset
> to all 1's and continued working from there. So I know the new
> bitstream was loaded and wasn't totally unreasonable. ;-)
>
So far I found lot of reports of similar problem - people load bitstream
with FSBL and it works. But when same bitstream is loaded from Linux access
to Ethernet is lost and something does happen on FPGA side. I'll explore
this further and I'll try to find more info.
> How would you like to troubleshoot this further? If necessary, I can
> connect a serial console and see what happens there, but I doubt it'd be
> of any help.
>
I have no idea... First I'll make new bitstream from beginning. I added
simple custom peripheral on current one to see if I'll be able to create
bitstream when I add other stuff except Parallella prototype (bitstream was
generated successfully). Deleting added stuff doesn't work as I expect it
so I'll start from scratch (BTW, I used backed up .bit file for generating
bin files I uploaded).
Katja
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