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Message-ID: <20261004105513.GZ3542221@port70.net>
Date: Sun, 4 Oct 2026 12:55:13 +0200
From: Szabolcs Nagy <nsz@...t70.net>
To: Alex Rønne Petersen <alex@...xrp.com>
Cc: musl@...ts.openwall.com
Subject: Re: [PATCH] riscv: declare all vector registers as clobbers
of syscalls
* Alex Rønne Petersen <alex@...xrp.com> [2026-10-04 04:48:52 +0200]:
> The kernel intentionally clobbers vector registers (by setting them to all 1s).
> musl didn't declare this, so with a compiler targeting the V extension, this
> could lead to all sorts of breakage that at first glance looks like
> miscompilations.
for the record the aarch64 behaviour is keeping the
normal parts of the simd regs and zeroing the sve
extension bits.
https://www.kernel.org/doc/html/latest/arch/arm64/sve.html#system-call-behaviour
so current musl clobber is wrong when compiled with +sve
(note: "cc" is actually preserved not clobbered)
test to demonstrate:
https://godbolt.org/z/xKfozYzjj
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