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Message-Id: <508e55a9-94ea-45fc-a0c5-03350705cef3@app.fastmail.com>
Date: Sun, 04 Oct 2026 10:08:28 +0200
From: Alex Rønne Petersen <alex@...xrp.com>
To: "Alexander Monakov" <amonakov@...ras.ru>, musl@...ts.openwall.com
Cc: "Rich Felker" <dalias@...c.org>
Subject: Re: [PATCH] riscv: declare all vector registers as clobbers of syscalls
On Sun, Oct 4, 2026, at 09:14, Alexander Monakov wrote:
> On Sun, 4 Oct 2026, Alex Rønne Petersen wrote:
>
>> > Is there a predefined macro that declares the availability of these
>> > registers that we could use? I really do not want to hard-code
>> > particular gcc or clang versions.
>>
>> Unfortunately no:
>>
>> $ riscv64-linux-gnu-gcc -march=rv64gc -dM -E - < /dev/null | grep __riscv
>
> But this is not the right test. You have to diff -E -dM from two runs, one with
> -march=rv64gc, another with -march=rv64gcv (and you'll find __riscv_vector).
I dismissed __riscv_vector initially because of these findings:
* GCC 12 defined __riscv_vector
* GCC 13+ understands v0-v31, vl, vtype
* GCC 14+ understands vxrm, vxsat
* Clang 12 defined __riscv_vector
* Clang 13+ understands v0-v31
* Clang 18+ understands vl, vtype, vxrm, vxsat
So that's all pretty horrible and makes __riscv_vector alone insufficient.
However, what we could do is a configure check that errors if __riscv_vector is defined but the clobbers we need aren't accepted. The user would then have to either disable V while building musl, or use GCC 14+ / Clang 18+. In that case, we could actually just rely on __riscv_vector in code.
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