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Message-ID: <024a17ed-766f-45cc-8c97-81ea414687c7@foss.arm.com>
Date: Thu, 29 Jan 2026 18:40:17 -0600
From: Bill Roberts <bill.roberts@...s.arm.com>
To: musl@...ts.openwall.com, Michael Morrell <mmorrell@...hyum.com>
Cc: "dalias@...c.org" <dalias@...c.org>, "dalias@...ifal.cx"
<dalias@...ifal.cx>, Bill Roberts <bill.roberts@....com>
Subject: Re: [PATCH v3] aarch64: rewrite fenv routines in C using
inline asm
On 1/29/26 3:57 PM, Michael Morrell wrote:
> +static inline uint32_t read_fpcr_u32(void) {
> + uint64_t x;
> + __asm__ volatile ("mrs %0, fpcr" : "=r"(x));
> + return (uint32_t)x;
> +}
> +
> +static inline void write_fpcr_u32(uint32_t v) {
> + uint64_t x = v;
> + __asm__ volatile ("msr fpcr, %0" :: "r"(x) : "memory"); }
> +
> +static inline uint32_t read_fpsr_u32(void) {
> + uint64_t x;
> + __asm__ volatile ("mrs %0, fpsr" : "=r"(x));
> + return (uint32_t)x;
> +}
> +
> +static inline void write_fpsr_u32(uint32_t v) {
> + uint64_t x = v;
> + __asm__ volatile ("msr fpsr, %0" :: "r"(x) : "memory"); }
> +
>
> Shouldn't the ending brace be on its own line for write_fpcr_u32 and write_fpsr_u32?
>
Yep, but I don't understand what happened as the patch shown here[1] on
the mailing list archive looks fine, as well as my local patch. Perhaps
something mangled it on your end? I also looked to see if any weird
non-ASCII chars got into the patch, I didn't see any, I see that line
ending with "; LF + } LF" or "3B 0A 2B 7D 0A" in hex.
1. https://openwall.com/lists/musl/2026/01/29/6
Thanks Michael,
Bill
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