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Message-ID: <20260116125740.158946-1-alex@alexrp.com>
Date: Fri, 16 Jan 2026 13:57:40 +0100
From: Alex Rønne Petersen <alex@...xrp.com>
To: musl@...ts.openwall.com
Cc: Alex Rønne Petersen <alex@...xrp.com>
Subject: [PATCH] riscv: don't define fenv macros for soft float
As is done for all other soft float ports.
---
arch/riscv32/bits/fenv.h | 5 +++++
arch/riscv64/bits/fenv.h | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/arch/riscv32/bits/fenv.h b/arch/riscv32/bits/fenv.h
index 806ec40f..2c126e6b 100644
--- a/arch/riscv32/bits/fenv.h
+++ b/arch/riscv32/bits/fenv.h
@@ -1,3 +1,7 @@
+#ifdef __riscv_float_abi_soft
+#define FE_ALL_EXCEPT 0
+#define FE_TONEAREST 0
+#else
#define FE_INVALID 16
#define FE_DIVBYZERO 8
#define FE_OVERFLOW 4
@@ -10,6 +14,7 @@
#define FE_DOWNWARD 2
#define FE_UPWARD 3
#define FE_TOWARDZERO 1
+#endif
typedef unsigned int fexcept_t;
typedef unsigned int fenv_t;
diff --git a/arch/riscv64/bits/fenv.h b/arch/riscv64/bits/fenv.h
index 806ec40f..2c126e6b 100644
--- a/arch/riscv64/bits/fenv.h
+++ b/arch/riscv64/bits/fenv.h
@@ -1,3 +1,7 @@
+#ifdef __riscv_float_abi_soft
+#define FE_ALL_EXCEPT 0
+#define FE_TONEAREST 0
+#else
#define FE_INVALID 16
#define FE_DIVBYZERO 8
#define FE_OVERFLOW 4
@@ -10,6 +14,7 @@
#define FE_DOWNWARD 2
#define FE_UPWARD 3
#define FE_TOWARDZERO 1
+#endif
typedef unsigned int fexcept_t;
typedef unsigned int fenv_t;
--
2.51.0
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