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Message-ID: <20adf11b-d19e-413a-ab7e-033b0f5f500e@isrc.iscas.ac.cn>
Date: Tue, 21 Oct 2025 11:05:00 +0800
From: Pincheng Wang <pincheng.plct@...c.iscas.ac.cn>
To: musl@...ts.openwall.com, nsz@...t70.net
Subject: Re: [PATCH 1/1] riscv: add Zacas extension support for atomic
CAS
On 2025/10/21 08:30, Szabolcs Nagy wrote:
> * Pincheng Wang <pincheng.plct@...c.iscas.ac.cn> [2025-09-19 00:47:20 +0800]:
>> Add compile-time detection for RISC-V Zacas extension and use
>> amocas.w.aqrl/amocas.d.aqrl instructions when available.
>>
>> When __riscv_zacas is defined, a_cas() and a_cas_p() use single amocas
>> instructions instead of lr/sc loops. Falls back to existing lr/sc
>> implementation when Zacas is not available.
>
> is this a supported extension? are there users?
> (implemented on existing cpus with released toolchain versions)
The Zacas extension was ratified in November 2023. CPUs such as the
XuanTie C930 already support this extension [1].
For toolchain support, GCC added Zacas extension support in commit
11c2453 ("RISC-V: Add basic support for the Zacas extension") on Jul 30,
2024.
Moreover, the RVA23 profile document [2] listed Zacas as a development
option and states that it "is intented to become mandatory in the future
RVA profile", suggesting broader adoption, particularly in
high-preformance computing domains such as PCs and servers, in the near
future.
[1] https://www.xrvm.com/product/xuantie/C930
[2]
https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf
> what cflags enable the extension? (how to test)
To enable this extension, use "-march=rv{32,64}gc_zacas" CFLAGS. In my
development environment, I'm using riscv64-unknown-linux-gnu-gcc
(version 15.1.0, commit g1b306039ac4) with the following configure command:
`CC=riscv64-unknown-linux-gnu-gcc CFLAGS="-march=rv64gc_zacas"
./configure --prefix=/home/wpcwzy/sysroot-rv64`
> i can't review if the instructions have the right semantics,
> but the code looks ok, with some comments below.
>
>>
>> Signed-off-by: Pincheng Wang <pincheng.plct@...c.iscas.ac.cn>
>> ---
>> arch/riscv32/atomic_arch.h | 17 +++++++++++++++++
>> arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++
>> 2 files changed, 47 insertions(+)
>>
>> diff --git a/arch/riscv32/atomic_arch.h b/arch/riscv32/atomic_arch.h
>> index 4d418f63..64ef05b7 100644
>> --- a/arch/riscv32/atomic_arch.h
>> +++ b/arch/riscv32/atomic_arch.h
>> }
>> +#ifdef __riscv_zacas
>
> newline before #ifdef
>
>> +#else /* Fallback to lr/sc when Zacas is not available */
> ...
>> +#endif /* __riscv_zacas */
>> \ No newline at end of file
>
> newline after endif
>
> i think ifdef comments are not needed in such a simple file.
>
Thank you for the formatting suggestions. I'll address these in the next
revision.
>> +++ b/arch/riscv64/atomic_arch.h
>> @@ -4,6 +4,34 @@ static inline void a_barrier()
>> __asm__ __volatile__ ("fence rw,rw" : : : "memory");
>> }
>>
>> +#ifdef __riscv_zacas
>> +
>> +#define a_cas a_cas
>> +static inline int a_cas(volatile int *p, int t, int s)
>> +{
>> + int old = t;
>> + __asm__ __volatile__ (
>> + "amocas.w.aqrl %0, %2, %1"
>> + : "+r"(old), "+A"(*(volatile int *)p)
>> + : "r"(s)
>> + : "memory");
>
> existing cas does not use +A constraint (check git log
> why and ensure this is ok).
>
> the ptr cast should not be needed. (same for rv32)
Thanks, I will review the git history and adjust the constraint and cast
in the next patch revision.
Best regards,
Pincheng Wang
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