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Message-ID: <20251013021847.GN1827@brightrain.aerifal.cx>
Date: Sun, 12 Oct 2025 22:18:47 -0400
From: Rich Felker <dalias@...c.org>
To: Alex Rønne Petersen <alex@...xrp.com>
Cc: musl@...ts.openwall.com
Subject: Re: [PATCH] s390x: shuffle register usage in __tls_get_offset
to avoid r0 as address register
On Mon, Oct 13, 2025 at 03:57:18AM +0200, Alex Rønne Petersen wrote:
> On Sun, Oct 12, 2025, at 17:33, Rich Felker wrote:
> > On Sun, Oct 12, 2025 at 05:35:19AM +0200, Alex Rønne Petersen wrote:
> >> This fixes an error in 6af4f25b899e89e4b91f8c197ae5a6ce04bcce7b: The r0 register
> >> is special in addressing modes on s390x and is interpreted as constant zero,
> >> i.e. lg %r5, 8(%r0) would effectively become lg %r5, 8. So care should be taken
> >> to never use r0 as an address register in s390x assembly.
> >> ---
> >> src/thread/s390x/__tls_get_offset.s | 14 +++++++-------
> >> 1 file changed, 7 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/src/thread/s390x/__tls_get_offset.s b/src/thread/s390x/__tls_get_offset.s
> >> index 405f118b..056c9110 100644
> >> --- a/src/thread/s390x/__tls_get_offset.s
> >> +++ b/src/thread/s390x/__tls_get_offset.s
> >> @@ -1,17 +1,17 @@
> >> .global __tls_get_offset
> >> .type __tls_get_offset,%function
> >> __tls_get_offset:
> >> - ear %r0, %a0
> >> - sllg %r0, %r0, 32
> >> - ear %r0, %a1
> >> + ear %r3, %a0
> >> + sllg %r3, %r3, 32
> >> + ear %r3, %a1
> >>
> >> la %r1, 0(%r2, %r12)
> >>
> >> - lg %r3, 0(%r1)
> >> - sllg %r4, %r3, 3
> >> - lg %r5, 8(%r0)
> >> + lg %r0, 0(%r1)
> >> + sllg %r4, %r0, 3
> >> + lg %r5, 8(%r3)
> >> lg %r2, 0(%r4, %r5)
> >> ag %r2, 8(%r1)
> >> - sgr %r2, %r0
> >> + sgr %r2, %r3
> >>
> >> br %r14
> >> --
> >> 2.48.1
> >
> > LGTM. This is just swapping use of r0 and r3, right? It seems to match
> > how gcc assigned things in my original disassembly of __tls_get_addr
> > when we discussed this the first time, and shouldn't have any
> > consequences on clobber contracts since it's the same registers being
> > used just for different purposes.
>
> That's exactly right. We've used all the volatile registers we have
> available according to the ABI, so swapping r0 and r3 usage seemed
> better than using a non-volatile register instead of r0 since we'd
> have to set up a stack frame at that point.
Thanks for confirming! Fix is pushed.
Rich
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