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Date: Wed, 8 Nov 2023 15:00:09 +0000
From: "Venkata Ramanaiah Nalamothu (QUIC)" <>
To: "" <>
Subject: RE: RISC-V 32bit port in MUSL upstream


-----Original Message-----
From: Venkata Ramanaiah Nalamothu (QUIC) 
Sent: Thursday, October 5, 2023 8:54 AM
Subject: RE: [musl] RISC-V 32bit port in MUSL upstream

Looks like that has changed and the ABI is being considered stable, otherwise GLIBC upstream wouldn't have accepted the RISC-V 32bit port, which is available since 2021 in GLIBC upstream.
As per [1],
     * Support for the RISC-V ISA running on Linux has been expanded to run on 32-bit hardware. This is supported for the following ISA and ABI pairs:
        - rv32imac ilp32
        - rv32imafdc ilp32
        - rv32imafdc ilp32d
       The 32-bit RISC-V port requires at least Linux 5.4, GCC 7.1 and binutils 2.28.

Ram Nalamothu


P.S: Apologies for the repost, the previous response was confusing because of the incorrect formatting.

-----Original Message-----
From: Markus Wichmann <> 
Sent: Friday, September 29, 2023 8:13 PM
Subject: Re: [musl] RISC-V 32bit port in MUSL upstream

WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.

Am Thu, Sep 28, 2023 at 04:39:37AM +0000 schrieb Venkata Ramanaiah Nalamothu (QUIC):
> Thank you very much for sharing the patch set/development branch.
> Looking at your github tree commit history, it seems the tree is actively maintained.
> May I know what is stopping from pushing these changes into MUSL community version?
> Were there any technical challenges or someone just need to find time to work with the community to get the changes reviewed/merged?

According to [0], main issue for Rich was that it was not a stable ABI yet back in 2020. Has that changed yet?



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