Date: Thu, 5 Oct 2023 03:12:41 +0000 From: "Venkata Ramanaiah Nalamothu (QUIC)" <quic_vnalamot@...cinc.com> To: "musl@...ts.openwall.com" <musl@...ts.openwall.com> Subject: RE: RISC-V 32bit port in MUSL upstream -----Original Message----- From: Markus Wichmann <nullplan@....net> Sent: Friday, September 29, 2023 8:13 PM To: musl@...ts.openwall.com Subject: Re: [musl] RISC-V 32bit port in MUSL upstream WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros. Am Thu, Sep 28, 2023 at 04:39:37AM +0000 schrieb Venkata Ramanaiah Nalamothu (QUIC): > Thank you very much for sharing the patch set/development branch. > > Looking at your github tree commit history, it seems the tree is actively maintained. > May I know what is stopping from pushing these changes into MUSL community version? > Were there any technical challenges or someone just need to find time to work with the community to get the changes reviewed/merged? According to , main issue for Rich was that it was not a stable ABI yet back in 2020. Has that changed yet? Looks like that has changed, otherwise GLIBC upstream wouldn't have accepted the RISC-V 32bit port, which is available since 2021 in GLIBC upstream. As per , * Support for the RISC-V ISA running on Linux has been expanded to run on 32-bit hardware. This is supported for the following ISA and ABI pairs: - rv32imac ilp32 - rv32imafdc ilp32 - rv32imafdc ilp32d The 32-bit RISC-V port requires at least Linux 5.4, GCC 7.1 and binutils 2.28. Regards, Ram Nalamothu  https://sourceware.org/pipermail/libc-alpha/2021-February/122207.html Ciao, Markus  https://www.openwall.com/lists/musl/2020/03/12/2
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