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Date: Mon, 10 Apr 2023 13:59:22 +0800 (GMT+08:00)
From: 张飞 <>
Subject: Re: Re: [PATCH]Implementation of strlen function in riscv64

I have made modifications to the assembly implementation of the riscv64 strlen function, mainly 
focusing on address alignment processing to avoid the problem of data crossing 
pages during vector instruction memory access.

I think the assembly implementation of strlen is necessary. In glibc, 
X86_64, aarch64, alpha, and others all have assembly implementations of this function, 
while for riscv64, it is blank.
I have also analyzed the test sets of Spec2006 and Spec2017, and the strlen function is also a hot topic.

Please review the patch again and look forward to your reply.

Fei Zhang

&gt; -----原始邮件-----
&gt; 发件人: "A. Wilcox" <>
&gt; 发送时间: 2023-03-22 14:27:33 (星期三)
&gt; 收件人:
&gt; 抄送: 
&gt; 主题: Re: [musl] [PATCH]Implementation of strlen function in riscv64 architecture
&gt; The content of the message was sent as an image.
&gt; For those who cannot view images, I've reproduced the text below:
&gt; On Mar 22, 2023, at 1:21 AM, 张飞 <> wrote:
&gt; &gt; 
&gt; &gt; Hi:
&gt; &gt; 
&gt; &gt; I implemented vectorization of the strlen function in the riscv64
&gt; &gt; architecture, which is controlled by __riscv_vector definition. Due
&gt; &gt; to lack of support for risc-v V expansion in hardware, I conducted
&gt; &gt; performance tests on a simulator, which was more than 10 times the
&gt; &gt; performance achieved in C language. In terms of functionality, I
&gt; &gt; tested the string length from 1 byte to 64 Mb, and the alignment of
&gt; &gt; different addresses at the beginning of the string.
&gt; &gt; 
&gt; &gt; 
&gt; &gt; Please review it.I'm Looking forward to your reply,thanks.
&gt; &gt; 
&gt; &gt; 
&gt; &gt; 
&gt; &gt; Fei Zhang
&gt; &gt; <strlen.s>

Download attachment "strlen_riscv64.patch" of type "application/octet-stream" (1323 bytes)

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