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Date: Thu, 16 Apr 2020 07:45:09 +1000
From: Nicholas Piggin <>
Cc:,,, Segher Boessenkool <>
Subject: Powerpc Linux 'scv' system call ABI proposal take 2

I would like to enable Linux support for the powerpc 'scv' instruction,
as a faster system call instruction.

This requires two things to be defined: Firstly a way to advertise to 
userspace that kernel supports scv, and a way to allocate and advertise
support for individual scv vectors. Secondly, a calling convention ABI
for this new instruction.

Thanks to those who commented last time, since then I have removed my
answered questions and unpopular alternatives but you can find them

Let me try one more with a wider cc list, and then we'll get something
merged. Any questions or counter-opinions are welcome.

System Call Vectored (scv) ABI

The scv instruction is introduced with POWER9 / ISA3, it comes with an
rfscv counter-part. The benefit of these instructions is performance
(trading slower SRR0/1 with faster LR/CTR registers, and entering the
kernel with MSR[EE] and MSR[RI] left enabled, which can reduce MSR 
updates. The scv instruction has 128 interrupt entry points (not enough 
to cover the Linux system call space).

The proposal is to assign scv numbers very conservatively and allocate 
them as individual HWCAP features as we add support for more. The zero 
vector ('scv 0') will be used for normal system calls, equivalent to 'sc'.


Linux has not enabled FSCR[SCV] yet, so the instruction will cause a
SIGILL in current environments. Linux has defined a HWCAP2 bit 
PPC_FEATURE2_SCV for SCV support, but does not set it.

When scv instruction support and the scv 0 vector for system calls are 
added, PPC_FEATURE2_SCV will indicate support for these. Other vectors 
should not be used without future HWCAP bits indicating support, which is
how we will allocate them. (Should unallocated ones generate SIGILL, or
return -ENOSYS in r3?)

Calling convention

The proposal is for scv 0 to provide the standard Linux system call ABI 
with the following differences from sc convention[1]:

- LR is to be volatile across scv calls. This is necessary because the 
  scv instruction clobbers LR. From previous discussion, this should be 
  possible to deal with in GCC clobbers and CFI.

- CR1 and CR5-CR7 are volatile. This matches the C ABI and would allow the
  kernel system call exit to avoid restoring the CR register (although 
  we probably still would anyway to avoid information leak).

- Error handling: I think the consensus has been to move to using negative
  return value in r3 rather than CR0[SO]=1 to indicate error, which matches
  most other architectures and is closer to a function call.

The number of scratch registers (r9-r12) at kernel entry seems 
sufficient that we don't have any costly spilling, patch is here[2].  


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