Date: Sun, 23 Feb 2020 18:08:25 +1100 (AEDT) From: Damian McGuckin <damianm@....com.au> To: musl@...ts.openwall.com Subject: Min and Max of 2 Floating Point numbers Curiosity only (i.e. not a MUSL question). But it is somewhat relevant to MUSL which I note at the end of this email. Besides the latest Intels, PowerPC, ARMs, I am just curious which of the CPU architectures implement this function directly at the assembler level, i.e. and hence avoiding a branch, i.e. double f .... double g .... and double fgmax = f > g ? f : g; The word 'implement' is a bit loose. I am not talking about the definition in Annex F of the C standard. The IEEE 754-2019 standard has changed the definition so as to properly propogate NaNs. The 1.2.0 version I just downloaded still follows the 2008 definition. ARM is smart enough to have 2 instructions, one (FMAX) which did propogate NaNs and one (FMAXNM) which follows the 2008 standard. That said, I do not personally compile on an ARM so I have no idea how you ask for FMAX or how you ask for FMAXNM? The PowerPC ISA 3.0 instruction properly propogates NaNs so it agrees with the new standard. The Intel instruction follows neither standard as far as I can tell. An interesting condition. Please tell me if I am wrong. MUSL relevance: I believe that even in 1.2.0, MUSL's own fmax/fmin libc routines violate the IEEE 754-2019 standard which came out recently. Well, it was approved June, published July, released November. I think that is recent. Regards - Damian Pacific Engineering Systems International, 277-279 Broadway, Glebe NSW 2037 Ph:+61-2-8571-0847 .. Fx:+61-2-9692-9623 | unsolicited email not wanted here Views & opinions here are mine and not those of any past or present employer
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