Date: Wed, 28 Feb 2018 11:43:05 +0100 From: Szabolcs Nagy <nsz@...t70.net> To: musl@...ts.openwall.com Subject: Re: clz instruction is unavailable for Thumb1 * Andre McCurdy <armccurdy@...il.com> [2018-02-27 19:00:58 -0800]: > On Tue, Feb 27, 2018 at 6:16 PM, Rich Felker <dalias@...c.org> wrote: > > On Tue, Feb 27, 2018 at 05:26:13PM -0800, Andre McCurdy wrote: > >> On Tue, Feb 27, 2018 at 5:01 PM, Rich Felker <dalias@...c.org> wrote: > >> > I forget what the situation with v6-m is, and whether/how it could be > >> > supportable. Is it really thumb1 or some thumb2 subset that fills > >> > deficiencies? > >> > >> It's Thumb1 plus BL, DMB, DSB, ISB, MRS and MSR from Thumb2. > > > > So that covers barrier but not atomics or thread pointer or syscalls, > > right? > > Thumb1 can make syscalls, but armv6-m has no atomics (the RTOS style > alternative being to disable interrupts around critical sections) and > no thread pointer (no coprocessors at all). > > > I'm not seeing how arm with only thumb1 plus the above can be a > > viable platform musl could run on, but maybe there are some kernel > > mechanisms to help..? > > I don't know if it's even possible to run a Linux kernel on these devices. > maybe this helps on linux: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8fcd6c45f5a65621ec809b7866a3623e9a01d4ed
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