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Date: Thu, 29 Jun 2017 13:59:26 -0400
From: Rich Felker <>
Subject: Re: [PATCH] powerpc64le: Add single instruction math functions

On Thu, Jun 29, 2017 at 01:00:51PM -0400, David Edelsohn wrote:
> >> A colleague of mine reminded me that ELFv2 ABI specifies POWER8 as the
> >> minimum hardware (not little-endian).
> >
> > This is a gratuitous requirement and has nothing to do with the
> > meaning of ELFv2 we're using (and likewise not with the gcc
> > --with-abi=elfv2).
> 2.1.1. Processor Architecture
> This ABI is predicated on, at a minimum, Power ISA version 2.7 and
> contains additional implementation characteristics.

Yes, I understand that it's there but this "requirement" is orthogonal
to the actual interface boundaries the ABI defines. ARM's EABI has a
similar gratuitous baseline of v4t; the compiler can satisfy all the
interface boundary requirements even on v4 and probably lower if it
wants to, but nobody has implemented that.

> >> The implementation of ELFv2 can
> >> operate on earlier hardware, but binaries may not be forward
> >> compatible because of VSX.  Because of the calling convention of VSX
> >> registers in ELFv2, the stack may be corrupted if an application built
> >> without VSX support is linked with a library that does support VSX.
> >> One cannot mix and match musl libc built for POWER4 or PPC970 and musl
> >> libc built for POWER7.
> >
> > I don't think this is accurate. If it is then it's a serious bug we
> > need to fix, and it should have been discussed at the time the port
> > was added...
> This is not an implementation detail in the library, it is the calling
> convention in the compilers.
> >
> > Can you provide a citation for the usage of VSX registers in the
> > calling convention, and how you think that affects the stack?
> Table 2.22 Vector Register Roles in Section Register Roles.
> The definition of volatile and non-volatile registers for vector
> registers affects the amount of stack allocated and the saving of
> non-volatile registers.

Are you saying the caller has to allocate space that the callee might
use to preseve call-saved registers it wants to use, and that the
amount saved depends on ISA level? If so I'll look for the associated
logic in GCC and see what it's doing. If that's the case it should be
reserving space regardless of whether it's built for an ISA level with
the registers or not.

> What is the status of the PPC64LE math optimization patch?

It's merged, I just forgot to push. So is the s390x one. Pushing now.


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