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Date: Fri, 7 Apr 2017 06:47:57 +0000
From: Jaydeep Patil <>
To: "" <>
Subject: RE: microMIPS32R2 O32 port

Hi Rich,

microMIPS is an Application Specific Extension (ASE) to MIPS cores. Both microMIPS and MIPS can co-exist. MIPS code can call microMIPS and vice-versa.
microMIPS is a compressed ISA and contains both 16 and 32-bit instructions for code size benefit. 

microMIPS revision R2 to R5 contains branch instructions with delay slot, however microMIPS revision R6 does not contain delay slots (B changed to BC). 
Assembler converts a B+NOP to BC when assembled for R6. Thus we have removed non-NOP instructions from the delay slot so that same code can be used for R6.


>-----Original Message-----
>From: Rich Felker [] On Behalf Of
>Sent: 06 April 2017 PM 09:48
>Subject: Re: [musl] [MUSL] microMIPS32R2 O32 port
>On Wed, Apr 05, 2017 at 06:33:01AM +0000, Jaydeep Patil wrote:
>> Hi Rich,
>> Please refer to
>> for
>> microMIPS32R2 O32 port. I have also attached the patch
>> (microMIPS32R2_v1_port.patch) for your reference.
>> Could you please review it?
>Some important first questions:
>Is micromips an ISA level or a new ISA? This is the same question as last time
>with MIPS r6 and the answer was not obvious and seemingly intentionally
>obscured by the official documentation. The answer is important to how we
>approach supporting it. Do cpus that support micromips also support plain
>mips? Is it like thumb where arm/thumb code can be linked together and call
>into one another in the same process, or are they different modes?
>Once we answer those questions, can you provide justifications for the
>proposed changes? From your patches it looks like branch delay slots don't
>exist in micromips mode. There may be other differences too; I didn't read it
>in detail. Rather than add a bunch of ifdefs I'd rather figure out how we can
>generalize the code so that it's compatible with both. This is what was done on
>arm when making it so the asm can be compiled as thumb2.

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