Date: Sun, 13 Mar 2016 09:54:58 +0900 From: Masanori Ogino <masanori.ogino@...il.com> To: musl@...ts.openwall.com Subject: Re: musl without atomic instructions? 2016-03-13 9:21 GMT+09:00 Rich Felker <dalias@...c.org>: > On Sun, Mar 13, 2016 at 08:47:36AM +0900, Masanori Ogino wrote: >> Hello, >> >> While I work on my GSoC proposal, I doubt whether musl can be built >> without hardware atomic operation supports. >> >> Could we build musl without such instructions? >> If we could, what will happen with the features of musl? > > Atomic compare and swap (usually provided by either a direct cas > instruction or ll/sc pair type) is a hard requirement for musl. OK, I understood. > The normal profiles of riscv have at least ll/sc style and possibly cas > too. Yes, ll/sc style primitives are provided in A standard extension, according to the ISA spec v2.0, section 5.3. > Minimal profiles for microcontroller use lack it (this was a > mistake in the riscv ISA specification, IMO), so if supporting these > ISA levels is interesting, there are at least three options: > > 1. Have the kernel trap the unimplemented instructions and emulate > them. > > 2. Have userspace issue a system call to have the kernel mediate > atomic accesses. > > 3. Integrate atomic sequence restart with the scheduler: at scheduling > time, the kernel determines if the task being resumed was > interrupted in the middle of a sequence of instructions that's > supposed to be atomic, and if so, resets the program counter to the > beginning of the sequence. (This is how pre-v6 ARM and most SH > models work.) > > Option 3 offers by far the best performance but inherently only works > on uniprocessor. Options 1 and 2 could theoretically support SMP as > long as the kernel has some other way of ensuring mutual exclusion and > memory synchronization between the processors. > > Of course the best of all worlds is to have the kernel provide a vdso > function for atomic cas which it can then provide an optimal > implementation of for the particular processor being used. Then > baseline-ISA-level riscv binaries would use the vdso, and ones > targeting an ISA level that's known to have native atomic instructions > would use the inline instructions. OK, I will ask about the current status on the RISC-V sw-dev ML. Thank you for clarification. -- Masanori Ogino
Powered by blists - more mailing lists
Confused about mailing lists and their use? Read about mailing lists on Wikipedia and check out these guidelines on proper formatting of your messages.