[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Sun, 15 Feb 2015 10:03:13 -0500
From: Rich Felker <dalias@...c.org>
To: Denys Vlasenko <vda.linux@...glemail.com>
Cc: musl <musl@...ts.openwall.com>
Subject: Re: [PATCH] x86_64/memset: use "small block" code for blocks
up to 30 bytes long
On Sun, Feb 15, 2015 at 03:07:06PM +0100, Denys Vlasenko wrote:
> On Sun, Feb 15, 2015 at 5:06 AM, Rich Felker <dalias@...c.org> wrote:
> >> The main change whose value I really question is the conditional
> >> widen_rax. If the value isn't used until a few cycles after the imul
> >> instruction, doing it unconditionally is probably cheaper than testing
> >> and branching even when the branch is predictable.
> >
> > To elaborate, simply replacing the unconditional imul with an
> > unconditional xor %eax,%eax in my best variant so far, I was only able
> > to save one cycle. So I don't see any way a test, branch, and
> > conditional imul could be less expensive than the unconditional imul.
>
> So imul elimination is a (tiny) win even on our CPUs, which happen
> to be the _fastest_ CPUs in regards to 64x64 imul (3 cycles).
No, it's a small (maybe you'd call it tiny) loss on them. That was my
point. It's only a tiny win when you rip out the conditional entirely
and just hard-code memset to always write zeros. (BTW, IIRC one OS had
a bug like that which went unnoticed for years... :)
> Just because we don't personally see a hit from 6-cycle imul of AMD CPUs,
> it does not mean people who do use those CPUs don't exist. Have heart...
Did you test the version I attached? I think there should be at least
4-5 cycles between when the imul is launched and when the result is
used, so I'm failing to see how the latency is a big deal.
Rich
Powered by blists - more mailing lists
Confused about mailing lists and their use?
Read about mailing lists on Wikipedia
and check out these
guidelines on proper formatting of your messages.
