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Date: Thu, 9 Jul 2020 09:22:09 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Andy Lutomirski <luto@...nel.org>
Cc: "Andersen, John" <john.s.andersen@...el.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Sean Christopherson <sean.j.christopherson@...el.com>,
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Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
X86 ML <x86@...nel.org>, "H. Peter Anvin" <hpa@...or.com>,
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Rick Edgecombe <rick.p.edgecombe@...el.com>,
Kristen Carlson Accardi <kristen@...ux.intel.com>,
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Greg KH <gregkh@...uxfoundation.org>, "Paul E. McKenney"
<paulmck@...nel.org>, Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
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"open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>, kvm list <kvm@...r.kernel.org>,
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Kernel Hardening <kernel-hardening@...ts.openwall.com>
Subject: Re: [PATCH 2/4] KVM: x86: Introduce paravirt feature CR0/CR4 pinning
On 7/9/20 9:07 AM, Andy Lutomirski wrote:
> On Thu, Jul 9, 2020 at 8:56 AM Dave Hansen <dave.hansen@...el.com> wrote:
>> On 7/9/20 8:44 AM, Andersen, John wrote:
>>> Bits which are allowed to be pinned default to WP for CR0 and SMEP,
>>> SMAP, and UMIP for CR4.
>> I think it also makes sense to have FSGSBASE in this set.
>>
>> I know it hasn't been tested, but I think we should do the legwork to
>> test it. If not in this set, can we agree that it's a logical next step?
> I have no objection to pinning FSGSBASE, but is there a clear
> description of the threat model that this whole series is meant to
> address? The idea is to provide a degree of protection against an
> attacker who is able to convince a guest kernel to write something
> inappropriate to CR4, right? How realistic is this?
If a quick search can find this:
> https://googleprojectzero.blogspot.com/2017/05/exploiting-linux-kernel-via-packet.html
I'd pretty confident that the guys doing actual bad things have it in
their toolbox too.
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