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Date: Tue, 27 Aug 2019 17:07:52 -0500
From: Scott Wood <oss@...error.net>
To: Jason Yan <yanaijie@...wei.com>
Cc: mpe@...erman.id.au, linuxppc-dev@...ts.ozlabs.org,
diana.craciun@....com, christophe.leroy@....fr,
benh@...nel.crashing.org, paulus@...ba.org, npiggin@...il.com,
keescook@...omium.org, kernel-hardening@...ts.openwall.com,
wangkefeng.wang@...wei.com, linux-kernel@...r.kernel.org,
jingxiangfeng@...wei.com, zhaohongjiang@...wei.com,
thunder.leizhen@...wei.com, fanchengyang@...wei.com,
yebin10@...wei.com
Subject: Re: [PATCH v6 04/12] powerpc/fsl_booke/32: introduce
create_tlb_entry() helper
On Fri, Aug 09, 2019 at 06:07:52PM +0800, Jason Yan wrote:
> Add a new helper create_tlb_entry() to create a tlb entry by the virtual
> and physical address. This is a preparation to support boot kernel at a
> randomized address.
>
> Signed-off-by: Jason Yan <yanaijie@...wei.com>
> Cc: Diana Craciun <diana.craciun@....com>
> Cc: Michael Ellerman <mpe@...erman.id.au>
> Cc: Christophe Leroy <christophe.leroy@....fr>
> Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>
> Cc: Paul Mackerras <paulus@...ba.org>
> Cc: Nicholas Piggin <npiggin@...il.com>
> Cc: Kees Cook <keescook@...omium.org>
> Reviewed-by: Christophe Leroy <christophe.leroy@....fr>
> Reviewed-by: Diana Craciun <diana.craciun@....com>
> Tested-by: Diana Craciun <diana.craciun@....com>
> ---
> arch/powerpc/kernel/head_fsl_booke.S | 29 ++++++++++++++++++++++++++++
> arch/powerpc/mm/mmu_decl.h | 1 +
> 2 files changed, 30 insertions(+)
>
> diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
> index adf0505dbe02..04d124fee17d 100644
> --- a/arch/powerpc/kernel/head_fsl_booke.S
> +++ b/arch/powerpc/kernel/head_fsl_booke.S
> @@ -1114,6 +1114,35 @@ __secondary_hold_acknowledge:
> .long -1
> #endif
>
> +/*
> + * Create a 64M tlb by address and entry
> + * r3/r4 - physical address
> + * r5 - virtual address
> + * r6 - entry
> + */
> +_GLOBAL(create_tlb_entry)
This function is broadly named but contains various assumptions about the
entry being created. I'd just call it create_kaslr_tlb_entry.
> + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
> + rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
> + mtspr SPRN_MAS0,r7 /* Write MAS0 */
> +
> + lis r6,(MAS1_VALID|MAS1_IPROT)@h
> + ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
> + mtspr SPRN_MAS1,r6 /* Write MAS1 */
> +
> + lis r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h
> + ori r6,r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l
> + and r6,r6,r5
> + ori r6,r6,MAS2_M@l
> + mtspr SPRN_MAS2,r6 /* Write MAS2(EPN) */
> +
> + ori r8,r4,(MAS3_SW|MAS3_SR|MAS3_SX)
> + mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
> +
> + tlbwe /* Write TLB */
> + isync
> + sync
> + blr
Should set MAS7 under MMU_FTR_BIG_PHYS (or CONFIG_PHYS_64BIT if it's
too early for features) -- even if relocatable kernels over 4GiB aren't
supported (I don't remember if they work or not), MAS7 might be non-zero
on entry. And the function claims to take a 64-bit phys addr as input...
MAS2_M should be MAS2_M_IF_NEEDED to match other kmem tlb entries.
-Scott
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