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Date: Sat, 13 Jan 2018 10:51:53 -0800
From: Linus Torvalds <>
To: Tony Luck <>
Cc: Dan Williams <>, 
	Linux Kernel Mailing List <>, Mark Rutland <>,, Peter Zijlstra <>, 
	Alan Cox <>, Will Deacon <>, 
	Alexei Starovoitov <>, Solomon Peachy <>, "H. Peter Anvin" <>, 
	Christian Lamparter <>, Elena Reshetova <>, 
	"" <>, Andi Kleen <>, 
	"James E.J. Bottomley" <>, Linux SCSI List <>, 
	Jonathan Corbet <>, "the arch/x86 maintainers" <>, Russell King <>, 
	Ingo Molnar <>, Catalin Marinas <>, 
	Alexey Kuznetsov <>, 
	Linux Media Mailing List <>, Tom Lendacky <>, 
	Kees Cook <>, Jan Kara <>, Al Viro <>,, Thomas Gleixner <>, 
	Mauro Carvalho Chehab <>, Kalle Valo <>, 
	Alan Cox <>, "Martin K. Petersen" <>, 
	Hideaki YOSHIFUJI <>, Greg KH <>, 
	Linux Wireless List <>, 
	"Eric W. Biederman" <>, Network Development <>, 
	Andrew Morton <>, "David S. Miller" <>, 
	Laurent Pinchart <>
Subject: Re: [PATCH v2 00/19] prevent bounds-check bypass via speculative execution

On Fri, Jan 12, 2018 at 4:15 PM, Tony Luck <> wrote:
> Here there isn't any reason for speculation. The core has the
> value of 'x' in a register and the upper bound encoded into the
> "cmp" instruction.  Both are right there, no waiting, no speculation.

So this is an argument I haven't seen before (although it was brought
up in private long ago), but that is very relevant: the actual scope
and depth of speculation.

Your argument basically depends on just what gets speculated, and on
the _actual_ order of execution.

So your argument depends on "the uarch will actually run the code in
order if there are no events that block the pipeline".

Or at least it depends on a certain latency of the killing of any OoO
execution being low enough that the cache access doesn't even begin.

I realize that that is very much a particular microarchitectural
detail, but it's actually a *big* deal. Do we have a set of rules for
what is not a worry, simply because the speculated accesses get killed
early enough?

Apparently "test a register value against a constant" is good enough,
assuming that register is also needed for the address of the access.


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