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Date: Sun, 27 Aug 2017 18:39:51 -0400
From: Boris Lukashev <>
To: Christopher Lameter <>
Cc: Ingo Molnar <>, Thomas Garnier <>, 
	Herbert Xu <>, "David S . Miller" <>, 
	Thomas Gleixner <>, Ingo Molnar <>, "H . Peter Anvin" <>, 
	Peter Zijlstra <>, Josh Poimboeuf <>, 
	Arnd Bergmann <>, Matthias Kaehlcke <>, 
	Boris Ostrovsky <>, Juergen Gross <>, 
	Paolo Bonzini <>, Radim Krčmář <>, 
	Joerg Roedel <>, Tom Lendacky <>, 
	Andy Lutomirski <>, Borislav Petkov <>, Brian Gerst <>, 
	"Kirill A . Shutemov" <>, "Rafael J . Wysocki" <>, 
	Len Brown <>, Pavel Machek <>, Tejun Heo <>, 
	Paul Gortmaker <>, Chris Metcalf <>, 
	Andrew Morton <>, 
	"Paul E . McKenney" <>, Nicolas Pitre <>, 
	Christopher Li <>, "Rafael J . Wysocki" <>, 
	Lukas Wunner <>, Mika Westerberg <>, 
	Dou Liyang <>, Daniel Borkmann <>, 
	Alexei Starovoitov <>, Masahiro Yamada <>, 
	Markus Trippelsdorf <>, Steven Rostedt <>, 
	Kees Cook <>, Rik van Riel <>, 
	David Howells <>, Waiman Long <>, Kyle Huey <>, 
	Peter Foley <>, Tim Chen <>, 
	Catalin Marinas <>, Ard Biesheuvel <>, 
	Michal Hocko <>, Matthew Wilcox <>, 
	"H . J . Lu" <>, Paul Bolle <>, Rob Landley <>, 
	Baoquan He <>, Daniel Micay <>, 
	"the arch/x86 maintainers" <>, Linux Crypto Mailing List <>, 
	LKML <>,, 
	kvm list <>, Linux PM list <>, 
	linux-arch <>,, 
	Kernel Hardening <>, 
	Linus Torvalds <>, Peter Zijlstra <>, 
	Borislav Petkov <>
Subject: Re: Re: x86: PIE support and option to extend
 KASLR randomization

On Fri, Aug 25, 2017 at 11:38 AM, Christopher Lameter <> wrote:
> On Thu, 17 Aug 2017, Boris Lukashev wrote:
>> Is the expectation then to have security functions also decrease size
>> and operational latency? Seems a bit unrealistic if so.
>> 1-2% performance hit on systems which have become at least several
>> hundred % faster over recent years is not a significant performance
>> regression compared to the baseline before.
> Where do you get these fantastic numbers? Where can I buy a system like
> that? Commonly we see regressions with single threaded integer
> performance on most newer processor generations.
> These hundreds of percent improvement can only come from floating point
> performance using specialized instructions. There are only a very limited
> number of applications that can make use of it.

An example of these fantastic numbers can be seen in which
shows a 9 year old P4 compared to today's desktop chips. Point taken
on the specific types of maths being performed though. I personally
can't make an educated guess at how much of the "modern" functionality
compilers could leverage to optimize these code paths.
I am by no means a chip or compiler architect, but have built a fair
number of systems and service oriented architectures; and in the
business-end of planning and design, a deficit of security function
doesn't just slow down execution by several percent - it can halt the
project or scuttle it altogether as stakeholders do not wish to put
their posteriors on the line.
The intent of my original email was to point out that the balance
between performance and security isn't as clear-cut as "all bugs are
created equal and hackbench outputs tell the whole story," since
aspects of performance and security are often evaluated by separate
parties in different segments of the decision making process.
Providing as many avenues as possible to enhance security posture with
clearly labeled performance penalties may be the difference between
adoption/execution and another cycle of "wait and see." While
decisions around future development agility based on changes in these
optional configurations are definitely a major point to consider, the
decision between a performance penalty and an exposed attack surface
is likely a useful option to leave for the people building the final


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