Date: Fri, 5 Apr 2013 15:13:37 -0700 From: Julien Tinnes <jln@...gle.com> To: "H. Peter Anvin" <hpa@...or.com> Cc: Ingo Molnar <mingo@...nel.org>, Kees Cook <keescook@...omium.org>, LKML <linux-kernel@...r.kernel.org>, "kernel-hardening@...ts.openwall.com" <kernel-hardening@...ts.openwall.com>, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, "x86@...nel.org" <x86@...nel.org>, Jarkko Sakkinen <jarkko.sakkinen@...el.com>, Matthew Garrett <mjg@...hat.com>, Matt Fleming <matt.fleming@...el.com>, Eric Northup <digitaleric@...gle.com>, Dan Rosenberg <drosenberg@...curity.com>, Will Drewry <wad@...omium.org> Subject: Re: [PATCH 3/3] x86: kernel base offset ASLR On Fri, Apr 5, 2013 at 3:08 PM, H. Peter Anvin <hpa@...or.com> wrote: > On 04/05/2013 03:06 PM, Julien Tinnes wrote: >> >> Speaking of IDT, and to capture some off-thread discussion here, we >> should remember that the "SGDT" and "SIDT" instructions aren't >> privileged on x86, so user-land can leak these out without any way for >> the kernel to intercept that. >> >> Adding their own random offsets to these two tables would be very >> useful. This could be done in a later patchset of course. >> > > Yes, if the GDT or IDT position is at all correlated to the kernel > position this is pointless. Let's say it's less useful :) Remote attacks and from-inside-a-VM attack would still be mitigated. Julien
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