Date: Thu, 04 Apr 2013 18:08:53 -0700 From: "H. Peter Anvin" <hpa@...or.com> To: Eric Northup <digitaleric@...gle.com> CC: Kees Cook <keescook@...omium.org>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, kernel-hardening@...ts.openwall.com, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, the arch/x86 maintainers <x86@...nel.org>, Jarkko Sakkinen <jarkko.sakkinen@...el.com>, Matthew Garrett <mjg@...hat.com>, Matt Fleming <matt.fleming@...el.com>, Dan Rosenberg <drosenberg@...curity.com>, Julien Tinnes <jln@...gle.com>, Will Drewry <wad@...omium.org> Subject: Re: [PATCH 3/3] x86: kernel base offset ASLR On 04/04/2013 01:47 PM, Eric Northup wrote: >> >> 1. actually compose the kernel of multiple independently relocatable >> pieces (maybe chunk it on 2M boundaries or something.) > > Without increasing the entropy bits, does this actually increase the # > of tries necessary for an attacker to guess correctly? It > dramatically increases the number of possible configurations of kernel > address space, but for any given piece there are only 256 possible > locations. > The 2M chunk was a red herring; one would of course effectively pack blocks together, probably packed back to back, in random order. >> 2. compile the kernel as one of the memory models which can be executed >> anywhere in the 64-bit address space. The cost of this would have >> to be quantified, of course. > > I attempted to do this, but was limited by my knowledge of the > toolchain. I would welcome help or suggestions! Start by looking at the ABI document. I suspect what we need is some variant of the small PIC model. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf.
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