Date: Fri, 11 Sep 2009 02:29:52 +0400 From: Solar Designer <solar@...nwall.com> To: john-users@...ts.openwall.com Subject: Re: asking what might happen in future releases On Thu, Sep 10, 2009 at 04:06:45PM +0200, rembrandt wrote: > Well I ment more stuff like the Markov-implementation. I do not intend to include the specific implementation that is currently in the jumbo patch. If I have time (which sounds unrealistic), I might do some testing, then either enhance the "incremental" mode or introduce a new cracking mode. > Threading or maybe even considering OpenCL implementation of some > algorithms. I just think that 8+ core CPUs gonna be avaiable > soon. Starting serval john-instances works, also if you combine it with > Markov but somehow it should get solved in a way which might be more > comfortable. So basically you're just pinging me to resume work on JtR, as usual. ;-) > Well would you asume some speedups during the 256bit SSE engines? I am not sure about the 256-bitness specifically - it may be twice faster than 128-bit "as it should be", or it may be the same, or it may be slower - depends on implementation (specific CPU). (For example, 128-bit SSE bitwise ops as originally implemented in Pentium 3 were actually slower than 64-bit MMX per-bit.) However, there are two other relevant improvements - 3-op instructions and the vpcmov instruction, which is similar to AltiVec/Cell vsel/selb. These are obviously usable for bitslice DES (and more), and in fact this has already been shown - I just happened to find that by doing a Google search for "vsel selb pcmov" (without the quotes) or something like that (I did several searches to confirm that the new instruction will in fact be similar to vsel/selb). Here's what I found: http://dango.chu.jp/hiki/?Bitslice+XOP Alexander
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