[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Tue, 4 Aug 2015 13:06:28 +0200
From: Agnieszka Bielec <bielecagnieszka8@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: PHC: Argon2 on CPU
2015-08-02 23:07 GMT+02:00 Lukas Odzioba <lukas.odzioba@...il.com>:
> 2015-08-02 22:46 GMT+02:00 Agnieszka Bielec <bielecagnieszka8@...il.com>:
>> even SSE4_1 but I don't know if only one instruction
>> blake2b-round.h:#define LOADU(p) _mm_loadu_si128( (__m128i *)(p) )
>> can make that it's SSE4_1 version (?)
>
> According to Intel's Intrinsics Guide:
> https://software.intel.com/sites/landingpage/IntrinsicsGuide/
> this is an intrinsics for SSE2 instruction, if this is what you are asking for.
> Also I guess that we should use unaligned access only where it is necessary.
however argon2 uses SSE4_1 because reaches file blake2b-load-sse-41.h
but I tested the speed with removed part with SSE4 and was the same
Powered by blists - more mailing lists
Confused about mailing lists and their use?
Read about mailing lists on Wikipedia
and check out these
guidelines on proper formatting of your messages.
