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Date: Wed, 14 Aug 2013 10:57:50 -0400
From: Yaniv Sapir <>
Subject: Re: Parallella: lclk_div

The clk divider is essential for the 16-core Parallella Prototype boards
that are configured with bitstreams released by Adapteva. However, the
lclk_div4 script is not used for quite some time, since the
e_reset_system() API resets the link registers. For this reason, we
re-program the link registers at the reset function, if a matching system
is detected - as defined in the HDF variable PLATFORM_VERSION.

It may be possible that a modified bitstream will render the system
unstable, if the Epiphany logic was modified, but this really requires
inspecting the change. What you could try is to change the PLATFORM_VERSION
to GENERIC and see if this works. I am not sure at the moment if this will
have other side-effects, though.


On Wed, Aug 14, 2013 at 9:29 AM, Solar Designer <> wrote:

> Yaniv -
> Regarding this comment by Roman:
> I am wondering whether this line:
> sudo /home/linaro/work/scr/lclk_div4.elf
> in rc.local on the Parallella prototype that we're using could actually
> be obsolete with the new bitstream and eSDK.  Should we keep it or
> should we remove it?  Can it be causing reliability problems (if kept?
> or if removed?)
> What is the purpose of this clock divider, and what does it do exactly?
> Thanks,
> Alexander

Yaniv Sapir
Adapteva Inc.
1666 Massachusetts Ave, Suite 14
Lexington, MA 02420
Phone: (781)-328-0513 (x104)
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