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Date: Fri, 9 Aug 2013 17:35:01 +0400
From: Solar Designer <>
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board


On Fri, Aug 09, 2013 at 03:29:11PM +0200, Katja Malvoni wrote:
> On Fri, Aug 9, 2013 at 2:02 PM, Sylvain Munaut <> wrote:
> > When rebuilding the kernel/device tree/fsbl, the device tree has some
> > issue with the PHY init that makes it work in gigabit mode only.
> >
> > See
> But this is for rebuilding fsbl, shouldn't Ethernet be intact when
> generating and replacing bitstream?

Sylvain is not on john-dev.

Please resend your message with CC to Sylvain.


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