Date: Fri, 9 Aug 2013 02:10:42 +0200 From: Katja Malvoni <kmalvoni@...il.com> To: john-dev@...ts.openwall.com Subject: ZedBoard / Parallella: bcrypt Hi Alexander, It seems that it's impossible to simulate Zedboard in ISim which will complicate this task a bit. I tried it with Parallella prototype and I wasn't able to make it work. There exists tutorial Hardware In The Loop (HIL) Simulation for the Zynq-7000 All Programmable SoC but it seems that it doesn't work with Zedboard. All I found on Xilinx and Zedboard forums was that it will be supported in future but it seems that support isn't ready yet ( http://forums.xilinx.com/t5/Embedded-Development-Tools/ZedBoard-HIL-simulation-problem-ELF-Verify-Failed/td-p/328467). But still, this requires physical access to board. Except that, there is AXI Bus Functional Model (BFM) used to simulate communication on AXI bus. I followed this tutorial http://zedboard.org/content/creating-custom-peripheral to create peripheral register (slightly changed to make it use BFM) and I was able to get everything in ISim. Although I still haven't figured out how to do actual simulation. Because of that I plan to do bcrypt implementation in following steps: - get working simulation of sbox transfers to and from custom peripheral (in this case custom peripheral will just store sbox) (in case I won't be able to do BFM simulation I'll skip this step) - implement those transfers between ARM core and FPGA on Parallella board - implement bcrypt's most costly loop as separate IP block and test it in ISim (without communication, just logic) - when I get working simulation test IP block with AXI BFM - merge with Parallella prototype Does this sound reasonable? Katja Content of type "text/html" skipped
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