Follow @Openwall on Twitter for new release announcements and other news
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Fri, 9 Aug 2013 13:17:50 +0400
From: Solar Designer <>
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board

On Thu, Aug 08, 2013 at 11:45:24PM +0200, Katja Malvoni wrote:
> On Thu, Aug 8, 2013 at 11:42 PM, Solar Designer <> wrote:
> > I think it's mostly ISE version difference.  I think a slightly older
> > version (14.4?) was used to generate Parallella's bitstream.
> There is one more difference between my design and reference design. In
> screen shot from
> utilisation for LUTs is 5%. In my project summary it's 6%. I
> guess zedboard templates differ in different ISE versions. That template is
> only thing not downloaded from official adapteva repo. I'll download ISE
> version used in reference design and try generating bitstream again.

Right.  Here's another thing you may try: with either/both ISE
version(s), you may generate not only Parallella's, but also ZedBoard's
original/demo bitstream.

With this, we won't be able to access Epiphany, but the rest should work
(including Ethernet), so it's a good test / sanity check.


Powered by blists - more mailing lists

Confused about mailing lists and their use? Read about mailing lists on Wikipedia and check out these guidelines on proper formatting of your messages.