Date: Thu, 8 Aug 2013 23:45:24 +0200 From: Katja Malvoni <kmalvoni@...il.com> To: john-dev@...ts.openwall.com Subject: Re: FPGA reprogramming on ZedBoard / Parallella board On Thu, Aug 8, 2013 at 11:42 PM, Solar Designer <solar@...nwall.com> wrote: > I think it's mostly ISE version difference. I think a slightly older > version (14.4?) was used to generate Parallella's bitstream. > There is one more difference between my design and reference design. In screen shot from http://www.adapteva.com/white-papers/parallella-platform-reference-design/implemented utilisation for LUTs is 5%. In my project summary it's 6%. I guess zedboard templates differ in different ISE versions. That template is only thing not downloaded from official adapteva repo. I'll download ISE version used in reference design and try generating bitstream again. Katja Content of type "text/html" skipped
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