Date: Sun, 9 Dec 2012 05:49:22 +0400 From: Solar Designer <solar@...nwall.com> To: john-dev@...ts.openwall.com Subject: Re: bitslice DES on GPU On Sun, Dec 09, 2012 at 05:34:03AM +0400, Solar Designer wrote: > You'd need to show (post in here) how you encoded the 0xf0000000 and > 0x0000000f constants in the kernels. Being a fairly large immediate > value, 0xf0000000 probably does not fit in one instruction's immediate > value field (GCN appears to use a 16-bit field for those, and a 12-bit > field for address offsets). Oh, there's also field code 255, which means "Literal constant", "32-bit constant from instruction stream". Apparently, this is precisely the case when a GCN instruction is 64-bit rather than 32-bit. This might apply to scalar rather than vector instructions only, though. It's page 52 in my AMD_Southern_Islands_Instruction_Set_Architecture.pdf. Anyhow, this: > On the other hand, 0x0000000f is small > enough to fit in an immediate offset field or even in a register number > field (GCN allows for encoding of values in the -16 to +64 range in that > way, via impossible register numbers). is sufficient to explain why you found no common offsets for the two different constants. Alexander
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