Date: Wed, 27 Apr 2016 19:55:14 +0000 (UTC) From: <apingis@...nwall.net> To: "john-dev@...ts.openwall.com" <john-dev@...ts.openwall.com> Subject: Re: USB-FPGA development On Wednesday, April 27, 2016 4:27 AM, Solar Designer <solar@...nwall.com> wrote: > I also think you may want to switch to implementing the actual password hashing (descrypt or/and bcrypt) along with your current I/O framework now (blocking functions), and only then approach improving the I/O. As mentioned above, I've already created descrypt application for FPGA and that works in simulator. That includes onboard hash comparsion. I estimate its performance at no less than 140 MH/s per chip (560 MH/s per board) and there's enough room for various optimizations. Now I'm planning to: - attach I/O; - create JtR format, develop JtR integration; - create on-chip candidate generator. I'm considering mask mode. Denis
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