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Date: Fri, 04 Sep 2015 12:59:23 +0200
From: magnum <>
Subject: Re: SHA-1 H()

On 2015-09-03 21:40, Solar Designer wrote:
> On Thu, Sep 03, 2015 at 09:29:37PM +0200, magnum wrote:
>> On 2015-09-03 20:40, Solar Designer wrote:
>>> I see you've committed this:
>>> +#if cpu(DEVICE_INFO) || amd_gcn(DEVICE_INFO)
>>> +#define HAVE_ANDNOT 1
>>> +#endif
>>> but I think the check for amd_gcn(DEVICE_INFO) is wrong.
>> We currently never run vectorized on GCN anyway, unless forced by user -
>> if format supports it at all.
> That's the SIMD vs. SIMT confusion again.

Oh, right :confused:.  That macro wouldn't have any effect though, since 
GCN has USE_BITSELECT. But I have now dropped it for GCN. Actually CPUs 
also got USE_BITSELECT so any sections for HAVE_ANDNOT are currently 
unused but I like to keep them there for the future.


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