Date: Wed, 29 Jul 2015 06:10:59 +0300 From: Aleksey Cherepanov <lyosha@...nwall.com> To: john-dev@...ts.openwall.com Subject: Re: Re: ztex 1.15y boards, pre-development On Mon, Jul 27, 2015 at 06:56:42PM +0200, Katja Malvoni wrote: > On 27 July 2015 at 18:15, Aleksey Cherepanov <lyosha@...nwall.com> wrote: > > > On Mon, Jul 27, 2015 at 06:02:03PM +0200, Katja Malvoni wrote: > > > On 27 July 2015 at 17:49, Aleksey Cherepanov <lyosha@...nwall.com> > > wrote: > > > > I tried to write several times and to write more in 1 pack (but not > > > > both). I get results only in fifth reading. So I removed printf and > > > > added cycle so: > > > > > > > > 5000 times: > > > > modify sent > > > > write 64 bytes > > > > read till length == 34 or up to 6 times > > > > fail if read 6 times > > > > check results > > > > > > > > It does not fail. 5k iteration take 6.1 seconds, so transfer speed is > > > > 52kb/s. Code attached. > > > > > > > > > > Cool! But I have one question: did you modify FPGA code? Because internal > > > FPGA buffer has size of 256 bits which is 32 bytes. Actually, now when I > > > look at host code, it seems you're writing 32 bytes, right? > > > > You're right: Above, I wrote "64 bytes" wrongly. It should be "32 > > bytes". I did not modify fpga code. > > > > So the speed is 26kb/s. > > > > I can reproduce the same behavior. I tried to modify your intraffic.v: I added SLRD_R <= 1'b1; into true branch of if (RESET == 1) begin This way I get correct results in the first read in the first run. On the second run and further, it behaves like above: correct results on 5th read. Thanks! -- Regards, Aleksey Cherepanov
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