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Date: Mon, 27 Jul 2015 18:02:03 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: Re: ztex 1.15y boards, pre-development
On 27 July 2015 at 17:49, Aleksey Cherepanov <lyosha@...nwall.com> wrote:
> On Mon, Jul 27, 2015 at 12:19:16PM +0300, Aleksey Cherepanov wrote:
> > On Mon, Jul 27, 2015 at 03:03:34AM +0300, Aleksey Cherepanov wrote:
> > > On Mon, Jul 27, 2015 at 02:54:14AM +0300, Aleksey Cherepanov wrote:
> > > > 4 runs lag remains.
> > >
> > > I think, I got how to bypass it: read 5 times and skip results from
> > > first 4 times. Also there is a difference: with wrong data I got 32
> > > bytes back, while good data come in 34 bytes "packet".
> > >
> > > I tried up to 20 reads, only fifth seem to be right.
>
> I tried to write several times and to write more in 1 pack (but not
> both). I get results only in fifth reading. So I removed printf and
> added cycle so:
>
> 5000 times:
> modify sent[]
> write 64 bytes
> read till length == 34 or up to 6 times
> fail if read 6 times
> check results
>
> It does not fail. 5k iteration take 6.1 seconds, so transfer speed is
> 52kb/s. Code attached.
>
Cool! But I have one question: did you modify FPGA code? Because internal
FPGA buffer has size of 256 bits which is 32 bytes. Actually, now when I
look at host code, it seems you're writing 32 bytes, right?
Thanks,
Katja
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