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Date: Mon, 27 Jul 2015 12:19:16 +0300
From: Aleksey Cherepanov <lyosha@...nwall.com>
To: john-dev@...ts.openwall.com
Subject: Re: Re: ztex 1.15y boards, pre-development
On Mon, Jul 27, 2015 at 03:03:34AM +0300, Aleksey Cherepanov wrote:
> On Mon, Jul 27, 2015 at 02:54:14AM +0300, Aleksey Cherepanov wrote:
> > 4 runs lag remains.
>
> I think, I got how to bypass it: read 5 times and skip results from
> first 4 times. Also there is a difference: with wrong data I got 32
> bytes back, while good data come in 34 bytes "packet".
>
> I tried up to 20 reads, only fifth seem to be right.
I've changed FIFO frequency from 30MHz to 48MHz in firmmare and delay
is 2 now, so I get correct data on third read after write. I added
bmBIT6 to IFCONFIG as documented here:
http://home.comcast.net/~traneus/dry0461.asm
But it says that it got 1024 bytes back always.
Thanks!
--
Regards,
Aleksey Cherepanov
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