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Message-ID: <20150726181221.GA716@openwall.com>
Date: Sun, 26 Jul 2015 21:12:22 +0300
From: Aleksey Cherepanov <lyosha@...nwall.com>
To: john-dev@...ts.openwall.com
Subject: Re: ztex 1.15y boards, pre-development
Katja,
On Sun, Jul 26, 2015 at 02:09:47PM +0300, Aleksey Cherepanov wrote:
> On Sun, Jul 26, 2015 at 02:01:35PM +0300, Aleksey Cherepanov wrote:
> > ztex-experimental$ java -cp ../ztex/java/FWLoader/FWLoader.jar FWLoader -uu t.ihx
> > s
> > FWLoader hangs here. Once I tried to turn off power of the board
> > quickly after start of the command and I got the following:
> > Firmware upload time: 126 ms
>
> Solved: I commented out
> EP6CS &= ~bmBIT0; // clear stall bit
>
> on line 44 in ez_transfer_data.c
http://wiki.ztex.de/doku.php?id=en:discussions:any_suggestions_on_where_to_look_for_the_bug_first
I can repeat your problem on my ztex.
I've replaced 2 lines in transfer_data.c to make failures more visible:
for(i = 0; i < 8; i++)
printf("S[0][%d] = 0x%08x 0x%08x %s\n", i, received[i], sent[i], received[i] == sent[i] ? "ok": "<<< failure");
But for me, it segfaulted first several runs and then it fails on every run:
S[0][0] = 0xd1310ba6 0xd131f12c <<< failure
S[0][1] = 0x98dfb5ac 0x98dfb5ac ok
S[0][2] = 0x2ffd72db 0x2ffd72db ok
S[0][3] = 0xd01adfb7 0xd01adfb7 ok
S[0][4] = 0xb8e1afed 0xb8e1afed ok
S[0][5] = 0x6a267e96 0x6a267e96 ok
S[0][6] = 0xba7c9045 0xba7c9045 ok
S[0][7] = 0xf12c7f99 0xf12c7f99 ok
Also I noticed that only 1 led on board became black, so I think only
1 fpga chip got bitstream.
My commands:
ztex-experimental$ java -cp ../ztex/java/FWLoader/FWLoader.jar FWLoader -uf test_communication/intraffic.bit
ztex-experimental$ gcc transfer_data.c -lusb && ./a.out
Thanks!
--
Regards,
Aleksey Cherepanov
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