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Message-ID: <20150707165016.GA10814@openwall.com>
Date: Tue, 7 Jul 2015 19:50:16 +0300
From: Solar Designer <solar@...nwall.com>
To: john-dev@...ts.openwall.com
Subject: Re: extend SIMD intrinsics
On Tue, Jul 07, 2015 at 11:22:54PM +0800, Lei Zhang wrote:
> On Jul 7, 2015, at 10:49 PM, Solar Designer <solar@...nwall.com> wrote:
> > On Tue, Jul 07, 2015 at 10:37:14AM +0800, Lei Zhang wrote:
> >> Using a union type, the pseudo-intrinsics would be written this way (for AltiVec):
> >>
> >> #vadd_epi32(x, y) (vtype)vec_add(x.v32, y.v32)
> >> #vadd_epi64(x, y) (vtype)vec_add(x.v64, y.v64)
> >>
> >> Does the type casting here violate strict aliasing?
> >
> > I find it weird. Why would you need it? Instead, assign the vec_*()
> > intrinsics outputs to .v fields.
>
> You mean, in-place updating like this(?):
>
> #vadd_epi32(z, x, y) z.v32 = vec_add(x.v32, y.v32)
>
> or just change the user code:
>
> z.v32 = vadd_epi32(x, y)
I have no preference between these two. I'll defer to magnum.
In DES_bs_b.c, it's the former (accepting the destination as a macro
parameter), so maybe we should do the same elsewhere for consistency.
> > More importantly, why are you proposing to define separate vector types
> > for different element sizes? I don't object to this, I merely ask.
> > There might be a good reason for it.
>
> For code just like the above:
>
> #vadd_epi32(z, x, y) z.v32 = vec_add(x.v32, y.v32)
> #vadd_epi64(z, x, y) z.v64 = vec_add(x.v64, y.v64)
Oh, OK. I think it's an AltiVec-specific thing that the same intrinsic
name corresponds to different vector element size depending on the type
of arguments.
> With a single vector type, they would be written like:
>
> #vadd_epi32(z, x, y) z.v = vec_add(x.v, y.v)
> #vadd_epi64(z, x, y) z.v = (vtype32)vec_add((vtype64)x.v, (vtype64)y.v)
>
> I think either way is fine. I just feel the former is clearer. Or maybe there's some better way than those two?
No, you're probably right.
Alexander
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