Date: Mon, 27 Apr 2015 06:12:25 +0300 From: Solar Designer <solar@...nwall.com> To: john-dev@...ts.openwall.com Subject: Re: [GSoC] JtR SIMD support enhancements On Mon, Apr 27, 2015 at 10:15:55AM +0800, Lei Zhang wrote: > IIRC, the current-generation MIC is using a low-power core design, based on the Atom series. It's based on Pentium (specifically, P54C) from 20 years back, even - but it's made 64-bit and has the 512-bit SIMD unit attached. https://software.intel.com/en-us/articles/intel-xeon-phi-core-micro-architecture "Many changes were made to the original 32-bit P54c architecture to make it into an Intel Xeon Phi 64-bit processor." BTW, this article on the microarchitecture describes several differences relative to Pentium that may be useful to us, including on possibly optimizing our bcrypt code to run better on Xeon Phi's scalar units - but we'll probably have to do that in assembler. Extrapolating from Pentium 120 MHz 20.4 c/s for hand-tuned asm: 20.4 * 60*1.053 / 0.12 = 10740 c/s Our current speed is twice worse: 10740/5339 = 2.01 Alexander
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