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Date: Sun, 20 Jul 2014 18:52:26 +0200
From: Katja Malvoni <>
Subject: Re: ZedBoard: bcrypt

On 20 July 2014 16:10, Katja Malvoni <> wrote:

>  On 20 July 2014 03:12, Solar Designer <> wrote:
>> What clock rate?
> 71 MHz as it was before (actually, it's a bit more: 71.4). Max frequency
> reported by Xilinx tool is 74.2 MHz but first higher than 71 MHz I can use
> is 76.9 MHz. It might work but I haven't tried it.

I generated bitstream with 76.9 MHz clock and timing score is 0. However,
it either locks up or reboots the zed system. After I run john, system
stops responding.

> I'll go for 5 BRAMs/instance with storing initial S-box values across
> unused halves of 4 BRAMs holding S-boxes. This way, initialization will
> require 256 clock cycles. I'm storing 2 S-boxes in higher half of each of 4
> BRAMs. Initialization data is stored twice but I can copy it in parallel
> for both instances. I don't use additional BRAMs and although utilization
> will be higher, it won't impact max core count (wider buses were used in
> 112 instances approach and core count was limited by available BRAM).

This is harder than it looks like... The first time I run john, first hash
is computed correctly and the next one is wrong (fails on get_hash[0](1).
After that, it fails on get_hash[0](0) and computed hash is different every
next run. If I reload the bitstream, computed hashes follow the same
pattern as in previous runs so it seems as initial S-box values have been
changed. However, in simulation initial values do not change during
computation and every time I store something to BRAM, I set only address
bits 8 to 0 to make sure only lower half is modified. Also, before anything
is assigned to address bus, it's set to 0 so bit 9 is zero anytime I write
to BRAM. I tried two approaches - using readmemh function with my code
which infers BRAM and using Coregen to generate IP cores with initial BRAM


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