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Date: Fri, 11 Apr 2014 18:54:39 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: ZedBoard: bcrypt
ᐧ
Hello,
Here are some better news about this.
Redesigning PS-PL communication resulted in improvement. I have working
design with 70 bcrypt cores. Performance is 2162 c/s on 71 MHz frequency. 2
cycles are needed for one Blowfish round. Computation on host is overlapped
with computation on FPGA 5/6th of the time.
Utilization is:
Number of Slice Registers: 11,849 out of 106,400 11%
Number of Slice LUTs: 44,811 out of 53,200 84%
Number of occupied Slices: 12,914 out of 13,300 97%
Number of RAMB36E1/FIFO36E1s: 140 out of 140 100%
Number of BUFG/BUFGCTRLs: 2 out of 32 6%
I can't fit more than 70 cores, BRAM is the limiting resource. If I don't
store P, expanded key, salt and cost in BRAM, I have to store it in
distributed RAM in order to keep the communication the way it is now. I
can't use AXI4 bus to store something in register, it has to be a memory
with address bus, data in and data out buses and write enable signal
(actually, when I implement it such that it uses write enable, it's
synthesized as distributed RAM. And write enable is the only way I can tell
is the host writing or reading). LUT utilization for this design was around
55% for 4 bcrypt cores.
Code: git clone https://github.com/kmalvoni/JohnTheRipper -b master
Katja
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