Date: Mon, 9 Sep 2013 21:48:33 +0200 From: Katja Malvoni <kmalvoni@...il.com> To: john-dev@...ts.openwall.com Subject: Re: ZedBoard / Parallella: bcrypt On Sun, Sep 8, 2013 at 10:15 AM, Katja Malvoni <kmalvoni@...il.com> wrote > The problem is that I don't know how else to communicate with PL. There is > no reference from Xilinx and connecting my logic to other RAM port was the > only way I could access data sent from host. Another way would be to make > second bram port external and than to connect it to user logic but still it > would use only one port. It took me a lot of time to figure out how to do > that communication and I really don't have any other idea except this one > There is another way but it still requires internal RAM. AXI4 interface supports master data transfers. Data is stored in fifo and depth of the fifo can be adjusted. But I wasn't able to make a successful transfer yet. I found out bug in verilog code and fixed it. Now it produces correct result for all test vectors. At the moment I'm using usleep(78125) instead of done signal - if done is put in shared bram than it is necessary to repeat DMA transfer until done is true. One possibility is to set up AXI4 data transfer in PL and have host read status register which is set after transfer finishes. But I'm not sure if this will work. Katja Content of type "text/html" skipped
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